View MC33304-D_4118394.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2000 august, 2000 rev. 1 1 publication order number: mc33304/d mc33304 low voltage rail-to-rail sleep-mode operational amplifier the mc33304 is a monolithic bipolar operational amplifier. this low voltage railtorail amplifier has both a railtorail input and output stage, with high output current capability. this amplifier also employs sleepmode technology. in sleepmode, the micropower amplifier is active and waiting for an input signal. when a signal is applied, causing the amplifier to source or sink 200 m a (typically) to the load, it will automatically switch to the awakemode (supplying up to 70 ma to the load). when the output current drops below 90 m a, the amplifier automatically returns to the sleepmode. excellent performance can be achieved as an audio amplifier. this is due to the amplifier's low noise and low distortion. a delay circuit is incorporated to prevent crossover distortion. ? ideal for battery applications ? full output signal (no distortion) for battery applications down to 0.9 vdc. ? single supply operation (+1.8 to +12 v) ? railtorail performance on both the input and output ? output voltages swings typically within 100 mv of both rails (r l = 1.0 m w ) ? two states: asleepmodeo (micropower, i d = 110 m a/amp) and aawakemodeo (high performance, i d = 1200 m a/amp) ? automatic return to sleepmode when output current drops below threshold, allowing a fully functional micropower amplifier ? independent sleepmode function for each amplifier ? no phase reversal on the output for overdriven input signals ? high output current (70 ma typically) ? 600 w drive capability ? standard pinouts; no additional pins or components required ? dropin replacement for many other quad operational amplifiers ? similar to mc33201, mc33202 and mc33204 family ? the mc33304 amplifier is offered in the plastic dip or soic package (p and d suffixes) http://onsemi.com marking diagrams a = assembly location wl = wafer lot yy, y = year ww = work week pdip14 p suffix case 646 1 14 so14 d suffix case 751a 1 14 1 14 mc33304p awlyyww 1 14 mc33304d awlyww device package shipping ordering information mc33304d so14 55 units/rail mc33304p pdip14 25 units/rail mc33304dr2 so14 2500 tape & reel pin connections (quad, top view) output 1 inputs 1 v cc output 4 inputs 4 1 12 13 14 11 3 2 1 4 10 5 9 6 output 2 8 7 inputs 2 2 4 3 v ee inputs 3 output 3
mc33304 http://onsemi.com 2 typical dc electrical characteristics (t a = 25 c) characteristic v cc = 2.0 v v cc = 3.3 v v cc = 5.0 v unit input offset voltage mv v io(max) mc33304 10 10 10 output voltage swing v oh (r l = 600 w ) 1.85 3.10 4.75 v min v ol (r l = 600 w ) 0.15 0.15 0.15 v max power supply current per amplifier (i d ) awakemode 1.625 1.625 1.625 ma sleepmode 140 140 140 m a specifications are for reference only and not necessarily guaranteed. v ee = gnd. maximum ratings rating symbol value unit supply voltage (v cc to v ee ) v s +16 v esd protection voltage at any pin human body model v esd 2000 v voltage at any device pin (note 2.) v dp v s 0.5 v input differential voltage range v idr (notes 1. and 2.) v output short circuit duration t s indefinite (note 3.) sec maximum junction temperature t j +150 c storage temperature range t stg 65 to +150 c maximum power dissipation p d (note 5.) mw recommended operating conditions characteristic symbol min typ max unit supply voltage v s v single supply 1.8 12 split supplies 0.9 6.0 input voltage range, sleepmode and awakemode v icr v ee v cc v ambient operating temperature range t a 40 +105 c 1. the differential input voltage of each amplifier is limited by two internal diodes. the diodes are connected across the input s in parallel and opposite to each other. for more differential input voltage range, use current limiting resistors in series with the input pins . 2. the commonmode input voltage range of each amplifier is limited by diodes connected from the inputs to both power supply rai ls. therefore, the voltage on either input must not exceed supply rail by more than 500 mv. 3. simultaneous short circuits of two or more amplifiers to the positive or negative rail can exceed the power dissipation ratin gs and cause eventual failure of the device. 4. railtorail performance is achieved at the input of the amplifier by using parallel npnpnp differential stages. when the in puts are near the negative rail (v ee < v cm < 800 mv), the pnp stage is on. when the inputs are above 800 mv (i.e. 800 mv < v cm < v cc ), the npn stage is on. this switching of the input pairs will cause a reversal of input bias current. slight changes in the input of fset voltage will be noted between the npn and pnp pairs. crosscoupling techniques have been used to keep this change to a minimum. 5. power dissipation must be considered to ensure maximum junction (t j ) is not exceeded. (see figure 2) 6. when connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the inverting input. this is because of the back to back diodes clamped across the inputs. the value of this resistor should be between 1.0 k w and 10 k w . if the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary. (the output could be tied directly to the negative input.)
mc33304 http://onsemi.com 3 dc electrical characteristics (v cc = +5.0 v, v ee = gnd, t a = 25 c, unless otherwise noted.) characteristic symbol min typ max unit input offset voltage (v cm = 0 v, v o = 0 v) (note 4.) sleepmode and awakemode t a = 25 c t a = 40 to +105 c v io 10 13 0.7 +10 +13 mv average temperature coefficient of input offset voltage (r s = 50 w , v cm = 0 v, v o = 0 v) t a = 40 to +105 c, sleepmode and awakemode d v io / d t 2.0 m v/ c input bias current (v cm = 0 v, v o = 0 v) (note 4.) awakemode t a = 25 c t a = 40 to +105 c ? i ib | 90 +200 +500 na input offset current (v cm = 0 v, v o = 0 v) (note 4.) awakemode t a = 25 c t a = 40 to +105 c |i io | 3.1 +50 +100 na large signal voltage gain (v cc = +5.0 v, v ee = 5.0 v) awakemode, r l = 600 w t a = 25 c t a = 40 to +105 c a vol 90 85 116 db power supply rejection ratio, awakemode psrr 65 90 db output short circuit current (awakemode) (v id = 0.2 v) source sink i sc 200 +50 89 +89 50 +200 ma output transition current, source/sink sleepmode to awakemode, v cc = +1.0 v, v ee = 1.0 v awakemode to sleepmode, v cc = +5.0 v, v ee 5.0 v |i th1 | |i th2 | 90 200 m a output voltage swing (v id = 0.2 v) sleepmode v cc = +5.0 v, v ee = 0 v, r l = 1.0 m w v cc = 0 v, v ee = 5.0 v, r l = 1.0 m w v cc = +2.0 v, v ee = 0 v, r l = 1.0 m w v cc = 0 v, v ee = 2.0 v, r l = 1.0 m w awakemode v cc = +5.0 v, v ee = 0 v, r l = 600 w v cc = 0 v, v ee = 5.0 v, r l = 600 w v cc = +2.0 v, v ee = 0 v, r l = 600 w v cc = 0 v, v ee = 2.0 v, r l = 600 w v cc = +2.5 v, v ee = 2.5 v, r l = 600 w v cc = +2.5 v, v ee = 2.5 v, r l = 600 w v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol 4.90 1.90 4.75 1.85 4.97 4.96 1.98 1.97 4.86 4.85 1.91 1.90 2.41 2.40 4.90 1.90 4.75 1.85 v common mode rejection ratio cmrr 60 90 db power supply current (per amplifier) sleepmode v cc = +2.0 v, v ee = 0 v t a = +25 c v cc = +2.5 v, v ee = 2.5 v t a = +25 c t a = 40 to +105 c v cc = +12 v, v ee = 0 v t a = +25 c awakemode v cc = +2.5 v, v ee = 2.5 v t a = +25 c t a = 40 to +105 c i d 85 110 125 1200 140 150 1625 1750 m a thermal resistance soic plastic dip q ja 145 75 c/w 4. railtorail performance is achieved at the input of the amplifier by using parallel npnpnp differential stages. when the in puts are near the negative rail (v ee < v cm < 800 mv), the pnp stage is on. when the inputs are above 800 mv (i.e. 800 mv < v cm < v cc ), the npn stage is on. this switching of the input pairs will cause a reversal of input bias current. slight changes in the input of fset voltage will be noted between the npn and pnp pairs. crosscoupling techniques have been used to keep this change to a minimum.
mc33304 http://onsemi.com 4 ac electrical characteristics (v cc = +6.0 v, v ee = 6.0 v, r l = 600 w , t a = 25 c, unless otherwise noted.) characteristic symbol min typ max unit slew rate (v cc = +2.5 v, v ee = 2.5 v, a v = +1.0) (note 6.) awakemode sr 0.5 0.89 v/ m s gain bandwidth product (f = 100 khz) awakemode gbw 2.2 mhz gain margin (c l = 0 pf) awakemode sleepmode (r l = 1.0 k w) a m 6.0 9.0 db phase margin (r l = 1.0 k w , v o = 0 v, c l = 0 pf) awakemode sleepmode f m 40 60 deg sleepmode to awakemode transition time r l = 600 w r l = 10 k t tr1 4.0 12 m sec awakemode to sleepmode transition time t tr2 1.5 sec channel separation (f = 1.0 khz) awakemode cs 100 db power bandwidth (v o = 4.0 v pp, r l = 2.0 k w , thd 1.0%) awakemode bw p 28 khz distortion (v o = 2.0 v pp , a v = +1.0) awakemode (f = 10 khz ) sleepmode (f = 1.0 khz, r l = infinite) thd 0.009 0.007 % open loop output impedance (v o = 0 v, f = 2.0 mhz, a v = +10, i q = 10 m a) awakemode sleepmode |z o | 100 1000 w differential input impedance (v cm = 0 v) awakemode sleepmode r in 200 1300 k w differential input capacitance (v cm = 0 v) awakemode sleepmode c in 8.0 0.4 pf equivalent input noise voltage (r s = 100 w , f = 1.0 khz) awakemode sleepmode e n 15 60 nv hz equivalent input noise current (f = 1.0 khz) awakemode sleepmode i n 0.22 0.20 pa hz 6. when connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the inverting input. this is because of the back to back diodes clamped across the inputs. the value of this resistor should be between 1.0 k w and 10 k w . if the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary. (the output could be tied directly to the negative input.)
mc33304 http://onsemi.com 5 figure 1. equivalent circuit block diagram (each amplifier) current threshold detector awake to sleepmode delay circuit awakemode current regulator sleepmode current regulator fractional load current detector i hysteresis i enable enable bias bias boost interface stage output stage input stage buffer c storage buffer overdrive correction v in % of i l i awake i sleep i bias i ref i l v out r l there are 515 active components for the entire quad device.
mc33304 http://onsemi.com 6 device description the mc33304 will begin to function at power supply voltages as low as v s = 0.8 v. the device has the ability to swing railtorail on both the input and the output. since the common mode input voltage range extends from v cc to v ee , it can be operated with either single or split voltage supplies. the mc33304 is guaranteed not to latch up or phase reverse over the entire common mode range. however, the output could go into phase reversal state if input voltage is set higher than +v cc or v ee . when power is initially applied, the part may start to operate in the awakemode. this occurs because of bias currents being generated from the charging of the internal capacitors. when this occurs, the user will have to wait approximately 1.5 seconds before the device will switch back to the sleepmode. the amplifier is designed to switch from sleepmode to awakemode whenever the output current exceeds a preset current threshold (i th ) of approximately 200 m a. as a result, the output switching threshold voltage (v st ) is controlled by the output loading resistance (r l ). large valued load resistors require a large output voltage to switch, but reduce unwanted transitions to the awakemode. most of the transition time is consumed slewing in the sleepmode until v st is reached, therefore, small values of r l allow rapid transition to the awakemode. the output switching threshold voltage (v st ) is higher for the larger values of r l , requiring the amplifier to slew longer in the slower sleepmode state before switching to the awakemode. although typically 200 m a, i th varies with supply voltage, temperature and the load resistance. generally, any current loading on the ouput which causes a current greater than i th to flow will switch the amplifier into the awakemode. this includes transition currents like those generated by charging load capacitances. in fact, the maximum capacitance that can be driven while attempting to remain in the sleepmode is approximately 300 pf. the awakemode to sleepmode transition time is controlled by an internal delay circuit, which is necessary to prevent the amplifier from going to sleep during every zero crossing of the output waveform. this delay circuit also eliminates the crossover distortion commonly found in micropower amplifiers. the mc33304 railtorail sleepmode operational amplifier is unique in its ability to swing railtorail on both the input and output using a bipolar design. this offers a low noise and wide common mode input voltage range. since the common mode input voltage range extends from v cc to v ee , it can be operated with either single or split voltage supplies. railtorail performance is achieved at the input of the amplifiers by using parallel npnpnp differential input stages. when the inputs are within 800 mv of the negative rail, the pnp stage is on. when the inputs are more than 800 mv above v ee , the npn stage is on. this switching of input pairs will cause a reversal of input bias currents. also, slight dif ferences in offset voltage may be noted between the npn and pnp pairs. crosscoupling techniques have been used to keep this change to a minimum. in addition to the railtorail performance, the output stage is current boosted to provide enough output current to drive 600 w loads. because of this high current capability, care should be taken not to exceed the 150 c maximum junction temperature specification.
mc33304 http://onsemi.com 7 mc33304p mc33304p , maximum power dissipation (mw) d(max) p -55 2.5 k t a , ambient temperature ( c) -40 -25 0 25 50 85 125 2.0 k 1.5 k 1.0 k 0.5 k 0 -55 150 i ib , input bias current (na) t a , ambient temperature ( c) v cc = +5.0 v v ee = gnd v cm = 0 v awakemode -40 -25 0 25 50 85 125 135 120 105 90 75 v cc = +5.0 v v ee = gnd r l = 600 w d v o = 0.5 to 4.5 v awakemode -55 130 a vol , open loop voltage gain (db) t a , ambient temperature ( c) 125 85 50 25 0 -25 -40 120 110 100 90 80 12 10 6.0 2.0 0 v cc , v ee supply voltage (v) 8.0 v o , output voltage (v ) pp 4.0 1.0 2.0 3.0 4.0 5.0 6.0 r l = 600 w - 1.0 m w t a = 25 c awakemode/ sleepmode 0.1 12 f, frequency (khz) v o , output voltage swing (v ) pp sleepmode (r l = 1.0 m w ) awakemode (r l = 600 w ) v cc = +6.0 v v ee = -6.0 v a v = +1.0 t a = 25 c 1.0 k 100 10 1.0 10 8.0 6.0 4.0 2.0 0 -6.0 100 i ib , input bias current (na) v cm , common mode input voltage (v) t a = 25 c v cc = +5.0 v v ee = gnd sleepmode awakemode -4.0 -2.0 0 2.0 4.0 6.0 50 0 -50 -100 -150 figure 2. maximum power dissipation versus temperature figure 3. input bias current versus temperature figure 4. input bias current versus common mode input voltage figure 5. open loop voltage gain versus temperature figure 6. output voltage swing versus supply voltage figure 7. output voltage versus frequency
mc33304 http://onsemi.com 8 10 100 v o , output voltage swing (v ) r l , load resistance to ground ( w ) figure 8. maximum peaktopeak output voltage swing versus load resistance v cc = +6.0 v v ee = -6.0 v f = 1.0 khz t a = 25 c pp 100 1.0 k 10 k 100 k 10 1.0 0.1 10 100 cmr, commom mode rejection (db) f, frequency (hz) figure 9. common mode rejection versus frequency v cc = +6.0 v v ee = -6.0 v t a = 25 c sleepmode awakemode 100 1.0 k 10 k 100 k 1.0 m 10 m 80 60 40 20 0 10 80 psr, power supply rejection (db) f, frequency (hz) figure 10. power supply rejection versus frequency v cc = +6.0 v v ee = -6.0 v t a = 25 c psr awakemode psr sleepmode 60 40 20 0 100 1.0 k 10 k 100 k 1.0 m 10 m 0 240 i th2 , current threshold ( a) m v cc , ? v ee ? , supply voltage (v) figure 11. awakemode to sleepmode current threshold versus supply voltage t a = 125 c t a = 25 c t a = -55 c source current 1.0 2.0 3.0 4.0 5.0 6.0 200 160 120 80 th1 , current threshold ( a) m 0 260 figure 12. sleepmode to awakemode current threshold versus supply voltage t a = 25 c t a = -55 c t a = 125 c source current v cc , ? v ee ? , supply voltage (v) 1.0 2.0 4.0 5.0 3.0 6.0 7.0 240 220 200 180 160 0 80 sc iv o i, output voltage (v) figure 13. output short circuit current versus output voltage v cc = +6.0 v v ee = -6.0 v v id = 1.0 v awakemode source sink 2.0 4.0 6.0 70 60 50 40 , output short circuit current (ma) i ?
mc33304 http://onsemi.com 9 supply current ( a) m i , d v cc = +2.5 v v ee = -2.5 v f = 100 khz gbw, gain bandwidth product (mhz) t a , ambient temperature ( c) 4.0 3.0 2.0 0 1.0 -55 -40 -25 25 70 125 0 85 105 source sink -55 120 t a , ambient temperature ( c) v cc = +5.0 v v ee = gnd v id = 0.2 v r l = 1.0 m w awakemode -40 -25 0 25 50 85 125 100 80 60 40 0 v cc , supply voltage (v) single supply r l = 600 w 3.5 7.0 10.5 14 3.0 k 2.0 k 1.0 k 0 4.0 k 0 600 single supply no load sleepmode ( m a) supply current ( a) m 2.0 4.0 6.0 8.0 10 12 14 500 400 300 200 100 0 -55 2.0 sr, slew rate (v/ s) m t a , ambient temperature ( c) v cc = +2.5 v v ee = -2.5 v v o = 2.0 v r l = 600 w + slew rate - slew rate -25 25 70 125 0 85 105 -40 1.5 1.0 0.5 0 10 14 a m , gain margin (db) r t , differential source resistance ( w ) v cc = +6.0 v v ee = -6.0 v r t = r1 + r2 v o = 0 v t a = 25 c sleepmode awakemode 100 1.0 k 10 k 12 10 8.0 6.0 4.0 2.0 0 figure 14. output short circuit current versus temperature figure 15. supply current versus supply voltage with load figure 16. supply current versus supply voltage figure 17. slew rate versus temperature figure 18. gain bandwidth product versus temperature figure 19. gain margin versus differential source resistance v , supply voltage (v) cc i , d sc , output short circuit current (ma) i
mc33304 http://onsemi.com 10 10 80 f m , phase margin ( ) r t , differential source resistance ( w ) sleepmode awakemode v cc = +6.0 v v ee = -6.0 v r t = r1 + r2 v o = 0 v t a = 25 c 10 k 1.0 k 100 70 60 50 40 30 20 10 10 70 phase margin ( ) c l , output load capacitance (pf) sleepmode awakemode 1.0 k 100 60 50 40 30 20 10 0 10 9.0 a c l , output load capacitance (pf) sleepmode awakemode v cc = +6.0 v v ee = -6.0 v 100 1.0 k 7.0 5.0 3.0 1.0 m , gain margin (db) 100 140 cs, channel separation (db) f, frequency (hz) v cc = +6.0 v v ee = -6.0 v r l = 600 w awakemode 1.0 k 10 k 100 k 120 100 80 60 40 20 0 100 100 thd, total harmonic distortion (%) f, frequency (hz) v cc = +6.0 v v ee = -6.0 v r l = 600 w v o = 2.0 v pp t a = 25 c awakemode a v = 1000 a v = 100 a v = 10 a v = 1.0 1.0 k 10 k 100 k 10 1.0 0.1 0.01 0.001 10 100 e n , input referred noise voltage (nv/ hz) f, frequency (hz) sleepmode awakemode v cc = +6.0 v v ee = -6.0 v t a = 25 c 100 k 10 k 1.0 k 100 80 60 40 20 10 figure 20. phase margin versus differential source resistance figure 21. gain margin versus output load capacitance figure 22. phase margin versus output load capacitance figure 23. channel separation versus frequency figure 24. total harmonic distortion versus frequency figure 25. input referred noise voltage versus frequency
mc33304 http://onsemi.com 11 10 1.4 i n , input noise current (pa/ hz) f, frequency (hz) figure 26. current noise versus frequency sleepmode awakemode v cc = +6.0 v v ee = -6.0 v t a = 25 c (r s = 100 k) 100 1.0 k 10 k 100 k 1.2 1.0 0.8 0.6 0.4 0.2 0 10 100 os, percent overshoot (%) c l , load capacitance (pf) figure 27. percent overshoot versus load capacitance v cc = +6.0 v v ee = -6.0 v t a = 25 c sleepmode (r l = ) awakemode (r l = 600 w ) 80 60 40 20 0 100 1.0 k
mc33304 http://onsemi.com 12 package dimensions pdip14 p suffix case 64606 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n t 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 so14 d suffix case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc33304 http://onsemi.com 13 notes
mc33304 http://onsemi.com 14 notes
mc33304 http://onsemi.com 15 notes
mc33304 http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33304/d sleepmode is a trademark of semiconductor components industries, llc (scillc). north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

▲Up To Search▲

Price & Availability of MC33304-D

	To Download MC33304-D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .